Current demands for high density and performance associated with ultra large scale integration require submicron features, increased transistor and circuit speeds, and improved reliability. Such demands require formation of device features with high precision and uniformity, which in turn necessitates careful process monitoring, including frequent and detailed inspections of the devices while they are still in the form of semiconductor wafers.
One important process requiring careful inspection is photolithography, wherein masks are used to transfer circuitry patterns to semiconductor wafers. Typically, a series of such masks are employed in a preset sequence. Each photolithographic mask includes an intricate set of geometric patterns corresponding to the circuit components to be integrated onto the wafer. Each mask in the series is used to transfer its corresponding pattern onto a photosensitive layer (e.g., a photoresist layer), which has been previously coated on a layer, such as a polysilicon or metal layer formed on the silicon wafer. An optical exposure tool such as a scanner or a stepper, which directs light or other radiation through the mask to expose the photoresist, conventionally performs the transfer of the mask pattern onto the photoresist layer. The photoresist is thereafter developed to form a photoresist mask, and the underlying polysilicon or metal layer is selectively etched in accordance with the mask to form features such as lines or gates.
Fabrication of the mask follows a set of predetermined design rules set by processing and design limitations. These design rules define the space tolerance between devices and interconnecting lines and the width of the lines themselves, to ensure that the devices or lines do not overlap or interact with one another in undesirable ways. Design rules set limits on critical dimensions (“CD”), which may be defined as any line width of interest in a device containing a number of different line widths. The CD for most features in ultra large scale integration applications is on the order of a fraction of a micron, however, it generally depends on the specific feature.
As design rules shrink and process windows (i.e., the margins for error in processing) become smaller, inspection and measurement of the surface features' profiles, which may include the surface features' CDs and sidewall angles, are becoming increasingly important. Deviations of a feature's CD and sidewall angle from design dimensions may adversely affect the performance of the finished semiconductor device, particularly the finished semiconductor device's drive current.
Accordingly, what is needed in the art is a simple, cost-effective methodology for fast and meaningful identification of a feature's profile variation, as well as correction of any drive current issues that might be associated with the variation.